1. Field of the Invention
The present invention generally relates to a memory device for multiplexing an input/output operation, and more specifically, to a memory device for multiplexing an input/output operation which prevents mis-operations by comparing the input addresses with the output data and improves operating speed by toggling input address to activate data corresponding to the input address if a valid address input detection signal is inputted late.
2. Description of the Prior Art
In general, a memory device becomes highly integrated and a chip size also becomes smaller.
For instance, since an input/output pad occupies a large area in the memory device, output data and input signals including input data and input addresses are multiplexed in order to reduce the number of input/output pads.
When the memory device multiplexes input/output operations, a valid address input detection signal is additionally used which becomes the basis of all timing.
As a result, when an address is toggled earlier than the address valid bar signal, an input address is recognized as invalid since a conventional art does not receive the input address before the address valid bar signal is activated.
When the address is toggled earlier than the address valid bar signal, the input address is recognized as valid and output data are also recognized as the input addresses, which results in large power consumption due to unnecessary operations and in mis-operations of the memory device.
In other words, when the memory device performs a asynchronous operation, all timing specification is set when an address is transitioned. As a result, when output data and an input address are not specified, output data are transmitted to an address buffer since the input address and the output data share an external data bus, and the memory device performs unnecessary operation due to the operation of the address buffer caused toggle of the output data, thereby causing unnecessary power consumption.